Pipelined RISC-V Processor

Problem

Overlapping five instructions in flight at once is what makes a pipeline fast, and also what breaks it: an instruction can read a register the one ahead of it has not written yet, and a taken branch invalidates whatever was speculatively fetched behind it.

Solution

A hazard unit that resolves both classes in hardware — forwarding results back from later stages, stalling when a load's value is not ready in time, and flushing the pipeline on a taken branch — so correct programs run without hand-inserted nops.

Overview

A 5-stage pipelined RISC-V processor built gate-by-gate in the Digital logic simulator. Instructions flow through fetch, decode, execute, memory, and writeback stages simultaneously, and a hazard unit resolves data and control hazards on its own by stalling, forwarding, and flushing — no manually inserted nop instructions required. Components include a 32-register register file, an ALU driven by the control unit, a branch unit that evaluates conditions and computes target addresses, and a load/store memory subsystem. Assembly test programs and Python tooling verify instruction behavior across the pipeline.

Impact

• ▸Assembly test programs and Python tooling verify instruction behavior across the pipeline.